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AMD Unveils “Zen 2” CPU Architecture and 7 nm Vega Radeon Instinct MI60 at New Horizon

AMD CEO Lisa Su displays a prototype 7nm 64-core Epyc CPU
AMD CEO Lisa Su displays a prototype 7nm 64-core Epyc CPU

AMD today held its “New Horizon” event for investors, offering guidance and “color” on what the company’s near-future could look like. At the event, the company formally launched its Radeon Instinct MI60 GPU-based compute accelerator; and disclosed a few interesting tidbits on its next-generation “Zen 2” mircroarchitecture. The Instinct MI60 is the world’s first GPU built on the 7 nanometer silicon fabrication process, and among the first commercially available products built on 7 nm. “Rome” is on track to becoming the first 7 nm processor, and is based on the Zen 2 architecture.

The Radeon Instinct MI60 is based on a 7 nm rendition of the “Vega” architecture. It is not an optical shrink of “Vega 10,” and could have more number-crunching machinery, and an HBM2 memory interface that’s twice as wide that can hold double the memory. It also features on-die logic that gives it hardware virtualization, which could be a boon for cloud-computing providers.

Shortly after unveiling its 7nm Radeon Instinct MI60 and MI50 accelerators at its Next Horizon Event, AMD revealed the company’s forthcoming EPYC ‘Rome’ processors. The new processors are built around the chipmaker’s Zen 2 CPU microarchitecture. They feature a new and revolutionary “chiplet” ecosystem whereby a 14nm I/O die sits at the center of the processor, surrounded by four 7nm CPU chiplet modules on each side. The chiplets are interconnected with the I/O die via AMD’s second-generation Infinity Fabric architecture. Each chiplet carries up to eight cores and 16 threads

If you’ve been paying attention to our “Zen 2” coverage over the past couple of weeks, you would’ve read our recent article citing a Singapore-based VLSI engineer claiming that AMD could disintegrate the northbridge for its high core-count enterprise CPUs, in an attempt to make the memory I/O “truly” wide, without compromising on the idea of MCM CPU chiplets. All of that is true.

“Rome” is codename for a multi-chip module of four to eight 7 nm CPU dies, wired to a centralized die over InfinityFabric. This 14 nm die, called “I/O die,” handles memory and PCIe, providing a monolithic 8-channel memory interface, overcoming the memory bandwidth bottlenecks of current-generation 4-die MCMs. The CPU dies and an I/O die probably share an interposer. Assuming each die has 8 CPU cores, “Rome” could have up to 64 cores, an 8-channel DDR4 memory interface, and a 96-lane PCI-Express gen 4.0 root-complex, per socket. If AMD has increased its core-count per CPU die, Rome’s core count could be even higher.

The broader memory I/O, assuming InfinityFabric does its job, could significantly improve performance of multi-threaded workloads that can scale across as many cores as you can throw at them, utilizing a truly broader memory interface. AMD also speaks of “increased IPC,” which bodes well for the client-segment. AMD has managed to increase IPC (per-core performance), with several on-die enhancements to the core design.

With “Zen” and “Zen+,” AMD recognized several components on the core that could be broadened or made faster, which could bring about tangible IPC improvements. This includes a significantly redesigned front-end. Zen/Zen+ feature a front-end that’s not much different than AMD’s past micro-architectures. The new front-end includes an improved branch-predictor, a faster instruction prefetcher, an improved/enlarged L1 instruction cache, and an improved prefetcher cache (L2).

The number-crunching machinery, the floating point unit, also receives a massive overhaul. “Zen 2” features 256-bit FPUs, which are doubled in width compared to Zen. load/store/dispatch/retire bandwidths have been doubled over the current generation. These changes are massive. Given that even without these core-level changes, by simply improving cache latencies, AMD managed to eke out a ~3% IPC uplift with “Zen+,” one can expect double-digit percentage IPC gains with “Zen 2.” Higher IPC, combined with possible increased core counts, higher clock speeds, and power benefits of switching to 7 nm, complete AMD’s “Zen 2” proposition.


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